The present invention relates to semiconductor memory devices used for semiconductor devices commonly referred to as chip-on-chip configuration semiconductor devices.
In the past, a semiconductor device in which a semiconductor chip is overlaid onto the surface of another semiconductor chip to be connected together has been proposed. When overlaying together, a pair of chip connector portions of the semiconductor chips that are overlaid to each other need to be aligned in advance between the semiconductor chips. When one of the semiconductor chips to be overlaid is a semiconductor memory device such as a DRAM, the chip connector portion of the semiconductor memory device is constructed according to the memory capacity, the bus width for data input and output, and the like, and therefore, the chip connector portion of the other semiconductor chip (master chip) to be overlaid is formed according to the configuration of the chip connector portion of the semiconductor memory device.
In a semiconductor memory device, when the data bus width or the voltage generated by a voltage generator provided inside is to be set, one of the mask options that have been provided in advance is selected or one of a plurality of fuses is cut off to fixedly set the data bus width or the generated voltage at a desired value.
Generally, a refresh operation for the data stored in a memory cell array of a semiconductor memory device is performed in such a manner that a sequential selection of memory cells is repeated so that all the memory cells are refreshed. Also, when data are written in memory cells in the memory cell array, a configuration generally employed is such that only one word line that intersects with a bit line is activated.
The foregoing conventional configurations, however, have at least the following drawbacks. When the specifications of the semiconductor memory device, such as memory capacities and bus widths for data input and output, are to be changed, that is, when the semiconductor memory device to be overlaid is of compilable type, design change is necessary for the chip connector portion of the semiconductor memory device and the chip connector portion of the master chip to be connected every time the specification is changed, in order to correspond to the change in the specifications, necessitating extra man-hours.
In addition, when selection of mask options or cutting off of a fuse is adopted in order to set data bus widths and generated voltages of the internal voltage generator of the semiconductor memory device to be incorporated, it is necessary to arrange those mask options and a plurality of fuses, increasing manufacturing steps and accordingly the cost.
Moreover, if a semiconductor memory device has memory cells having a region that does not require a data holding operation during a refresh operation of the memory cells, the conventional configuration in which all the memory cells are refreshed is inefficient in terms of power consumption. Furthermore, the conventional configuration in which only one word line that intersects with a bit line is activated when data are written in a memory cell has a drawback that, for example, when performing a burn-in test, a long time is required to write data into all the memory cells and the efficiency of the test is poor.